Memory devices include an array of memory cells that are read by sensing the voltage or charge stored by the memory cells. The memory cells are typically coupled through one or more bit lines to a sensing circuit that performs the function of sensing the voltage or stored charge. For example, in a NAND flash memory array, such as a NAND flash memory array 10 shown in FIG. 1, the array 10 is comprised of a large number of flash memory cells, collectively indicated by reference numeral 14. The array of flash memory cells 14 is typically divided into a number of blocks, one of which is shown in FIG. 1. Each block includes a number of rows, which, in the example shown in FIG. 1, includes 32 rows. The cells 14 in the same row have their control gates coupled to a common word line 30, each of which receives a respective word line signal WL0-WL31.
As also shown in FIG. 1, the cells 14 in the same column have their sources and drains connected to each other in series. Thus all of the memory cells 14 in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell 14 in the block is coupled to a bit line 20 through a first select gate transistor 24. The conductive state of the transistors 24 in each block are controlled by a source gate SG(D) signal. Each of the bit lines 20 output a respective bit line signal indicative of the data bit stored in the respective column of the array 10. The source of the lower flash memory cell 14 in the block is coupled to a source line 26 through a second select gate transistor 28. The conductive state of the transistors 28 in each block are controlled by a source gate SG(S) signal. The source line 26 receives a signal SL having various magnitudes depending upon whether the memory cells 14 are being programmed, i.e., data are being written in the cells 14, read or erased.
A read operation is performed on a row-by-row basis. When a read operation is to be performed for a selected block, the source line 26 is coupled to ground, and the select gate transistors 24, 28 for that block are turned ON responsive to high SG(D) and SG(S) signals. Also, the bit line 20 for each column is precharged. The bit line 20 is precharged by applying a high PRE signal to the gates of respective NMOS transistors 40 thereby coupling a supply voltage VCC to a drain of respective NMOS clamp transistors 42. The gates of the transistors 42 receive a clamp voltage BLCLMP that sets the precharge voltage of the bit lines 20 to BLCLMP less the threshold voltage VT of the transistors 42. Although NMOS clamp transistors 40, 42 are used in the embodiment shown in FIG. 1, other devices, such as PMOS transistors, may alternatively be used.
After the bit lines have been precharged, a read voltage is applied to a word line 20 for the selected row, thereby applying the read voltage to the control gates of all of the flash memory cells 14 in that row. As explained above, the magnitude of the read voltage is sufficient to turn ON all flash memory cells 14 that do not have a sufficiently charged floating gate, but insufficient to turn ON all cells that have a sufficiently charged floating gate. A voltage having a higher magnitude is applied to the word lines 20 for all of the non-selected rows. This voltage is large enough to turn ON the flash memory cells 14 even if their floating gates are storing sufficient charge to be read as programmed. As a result, the bit line 20 voltage for each column will be lowered if the cell 14 in that column of the selected row is not storing enough charge to turn OFF the device at that gate bias. Otherwise the bit line 20 remains high at VCC.
The voltage on each bit line 20 during a read operation is applied to a gate of a respective NMOS output transistor 44 through an NMOS clamp transistor 42. The drain of the output transistor 44 is biased to VCC or another voltage through a PMOS transistor 46 or other device. If the bit line 20 has been pulled low responsive to all of the memory cell 14 in the column being conductive, the output transistor 44 for that column will be turned OFF, thereby allowing the input to a latch 48 to be driven to VCC through the transistor 46. This voltage is sampled by the latch 48 responsive to a sense enable SE signal. Once the drain of the output transistor 44 is sampled responsive to the SE signal, the latch 48 will output a “1” binary value. If, on the other hand, the memory cell 14 being read remains non-conductive, the bit line 20 will remain at its precharged level. The output transistor 44 for that column will therefore be turned ON, thereby driving the input to the latch 48 low. As a result, once the drain of the output transistor 44 is sampled responsive to the SE signal, the latch 48 will output a “0” binary value.
The speed at which a memory cell 14 can be read is often of critical importance in the performance of a memory device. The time required to read a memory cell 14 is greatly affected by the rate at which change in the voltages of the bit lines 20 can be sensed by the respective output transistors 44. The bit lines 20 are essentially transmission lines that can be represented by a long series of resistors with a capacitor coupled to ground between each pair of interconnected resistors. As a result of this capacitance coupled with the often high resistance of the bit lines 20, the voltage at the gates of the output transistors 44 changes fairly gradually responsive to a column of memory cells 14 becoming conductive. With the increased size of memory arrays and smaller geometries, which result in narrower and hence higher bit line resistances and greater bit line capacitances, these delays can become even longer. Furthermore, the rate at which the voltage at a bit line falls responsive to a string of memory cells 14 becoming conductive is a function of the length of the bit line 20 between the output transistor 44 and an active block of memory cells having the conductive string of memory cells 14. As the active block of memory cells 14 becomes further from the output transistors 44, the rate at which the voltage at the gates of the output transistors 44 fall becomes more gradual. For example, with reference to FIG. 2, the PRE signal transitions high and the BLCLMP signal transitions to an initial clamp voltage blclmpi at 0.5 μs, thereby precharging the bit line 20 to a voltage that is equal to blclmpi less the threshold voltage VT of the clamp transistor 42. The BLCLMP signal transitions to zero at 6.5 μs, and a conductive string of memory cells 14 then begins discharging the bit line 20. The BLCLMP signal transitions to a final clamp voltage blclmpf at 8.5 μs, and remains there during the remainder of the reading process. FIG. 2 shows the voltage of the bit line 20 responsive to conductive memory cells strings in four different blocks of memory cells 14 at increasing distances from the output transistor 44, which results in increasing lengths of the bit line 20 connecting the active memory to the output transistor 44. The discharge of the relatively short length of the bit line 20 for the closest block is at a fairly rapid rate 50, and the discharge of the relatively long length of the bit line 20 for the farthest block is at a substantially slower rate 52. The intermediate length bit lines 20 for the intermediate blocks discharge at intermediate rates 54, 56. As a result, when the latch 48 is enabled by the SA signal starting at 13.5 μs, the bit line 20 discharged at rates 52, 56 has a voltage that is greater than the threshold voltage VT of the output transistor 44 while the bit line 20 discharged at rates 50, 54 has a voltage that is less than the threshold voltage VT of the output transistor 44. The bit line 20 discharged at rates 52, 56 is therefore incorrectly sampled as a logic “1” while the bit line 20 discharged at rates 50, 54 is correctly sampled as a logic “0.”
There is therefore a need for a circuit and method for sampling the bit lines of a memory device that can, for example, compensate for the variations in the rate at which the voltages at the gates of the output transistors 44 change as a function of distance that the active block is spaced from the output transistors 44.